The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs. Each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and lowering associated costs.
In recent decades, the chemical mechanical polishing (CMP) process has been used to planarize layers used to build up ICs, thereby helping to provide more precisely structured device features of the ICs. The CMP process is a planarization process that combines chemical removal with mechanical polishing. The CMP process is a favored process because it achieves global planarization across the entire wafer surface. The CMP polishes and removes materials from the wafer, and works on multi-material surfaces.
Since the CMP process is one of the important processes for forming ICs, it is desired to have mechanisms to maintain the reliability and the efficiency of the CMP process.